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Advanced Computer Architecture: 11th Conference, ACA 2016, by Junjie Wu, Lian Li PDF

By Junjie Wu, Lian Li

ISBN-10: 9811022089

ISBN-13: 9789811022081

ISBN-10: 9811022097

ISBN-13: 9789811022098

This publication constitutes the refereed complaints of the eleventh Annual convention on complicated desktop structure, ACA 2016, held in Weihai, China, in August 2016.

The 17 revised complete papers awarded have been conscientiously reviewed and chosen from 89 submissions. The papers handle concerns resembling processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and information facilities; power and reliability; intelligence computing and cellular computing.

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Extra info for Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings

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In: IEEE Symposium on High-Performance Computer Architecture, pp. 50–61 (2011) 4. : Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. ACM Trans. Des. Autom. Electron. Syst. 19 (1), 1–23 (2013) 5. : Optimizing band width and power of graphics memory with hybrid memory technologies and adaptive data migration. In: Proceedings of the International Conference Computer-Aided Design, pp. 81–87 (2012) 6. NVSim. php 7. : Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems.

Runtime power-down strategies for real-time SDRAM memory controllers. In: Proceedings of the 49th Annual DAC, pp. 988–993. ACM (2012) 12. : Online memory compression for embedded systems. ACM Trans. Embed. Comput. Syst. 9, 1–30 (2010) 13. : The filter cache: an energy efficient memory structure. In: 30th International symposium on Microarchitecture (MICRO), pp. 184–193 (1997) 14. : Non-uniform power access in large caches with low-swing wires. In: International Conference on High Performance Computing (HiPC).

However, if there is a write access to the block, both its refresh-counter and access-counter are initialized to 0. The maximum value of refresh-counter Nmax depends on their different retention time. When a LRS or MRS block’s Nref reaches Nmax , we do not conduct a refresh operation but check its 34 H. Zhang et al. Fig. 5. The counter-based writeback refresh scheme Nac . We write it back to HR-Region in case of Nac [ 5, otherwise write it back to main memory. The whole scheme shown in Fig. 5 is called Counter-based Writeback Refresh Scheme (CWRS).

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Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings by Junjie Wu, Lian Li

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