By Manuel F. M. Barros, Jorge M. C. Guilherme, Nuno C. G. Horta (auth.)
The microelectronics industry developments current an ever-increasing point of complexity with exact emphasis at the construction of advanced mixed-signal systems-on-chip. Strict financial and layout pressures have pushed the advance of recent the way to automate the analog layout technique. in spite of the fact that, and regardless of a few major learn efforts, the basic act of layout on the transistor point remains to be played via the trial and blunder interplay among the fashion designer and the simulator.
This booklet offers a brand new layout automation method in accordance with a converted genetic set of rules kernel, to be able to enhance potency at the analog IC layout cycle. The proposed technique combines a strong optimization with nook research, computing device studying innovations and allotted processing strength in a position to care for multi-objective and restricted optimization difficulties. The ensuing optimization software and the development in layout productiveness is tested for the layout of CMOS operational amplifiers.
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Extra info for Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
3 can be evaluated by several metrics that measure the final solution quality. The first column “date” is performance independent. There is no correlation between the availability of the design tool and its efficiency or accuracy. On the contrary, the next three characteristics columns “Evaluation Class”, “Algorithm Techniques” and “Equation/Design Plan”, which are often used for classification purposes, will have an important influence in the performance and accuracy as will be shown later in this chapter.
Finally, conclusions concerning the specification and design of a new analog design automation methodology implementation will be drawn. 1 Trends in Design Automation Methodology A typical design flow for analog and mixed-signal IC circuits (AMS) consists of a series of design steps repeated from the system level to the device-level, and bottom-up for layout generation and verification. The steps between any two of these hierarchical levels are: topology selection, circuit sizing, design verification and layout generation task, illustrated in Fig.
Moreover, within this approach the same circuit can be optimized several times for different specs as long as the goal function is adapted, therefore, with this approach virtually all types of circuits can be sized and optimized with low setup time. Despite these advantages, automated circuit sizing is not as commonly used as for example, circuit simulation, since it is computationally too expensive to evaluate electrical simulations. However, with the exponential increase of computer 30 Analog Cir.
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques by Manuel F. M. Barros, Jorge M. C. Guilherme, Nuno C. G. Horta (auth.)